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crystal-to-3.3v lvpecl frequency synthesizer ics843004-02 idt ? / ics ? 3.3v lvpecl frequency synthesizer 1 ics843004AG-02 rev a july 30,2007 g eneral d escription the ics843004-02 is a 4 output lvpecl synthesizer optimized to generate clock frequencies for a variety of high performance applications and is a member of the hiperclocks tm family of high performance clock solutions from idt. this device can select its input reference clock from either a crystal input or a single-ended clock signal and can be configured to generate a number of different output frequen- cies via the 3 frequency select pins (f_sel2:0). the ics843004-02 uses idt? 3rd generation low phase noise vco technology and can achieve 1ps or lower typical rms phase jitter. this ensures that it will easily meet clocking requirements for high-speed communication protocols such as 10 and 12 gigabit ethernet, 10 gigbit fibre channel, and sonet. this device is also suitable for next generation serial i/ o technologies like serial ata and scsi and is conveniently packaged in a small 24-pin tssop package. f eatures ? four 3.3v lvpecl outputs ? selectable crystal oscillator interface or lvcmos/lvttl single-ended input ? output frequency range: 70mhz - 680mhz ? crystal input range: 14mhz - 37.78mhz ? vco range: 560mhz - 680mhz ? supports the following applications: fibre channel, sonet, ethernet, serial ata, scsi and hdtv ? rms phase jitter @ 155.52mhz (12khz - 20mhz): 0.91ps (typical) offset noise p o w er 100hz ............... -97.1 dbc/hz 1khz ............. -121.6 dbc/hz 10khz ......... .... -124.9 dbc/hz 100khz ......... .... -125.1 dbc/hz ? full 3.3v supply mode ? 0c to 70c ambient operating temperature ? available in both standard and lead-free rohs compliant packages hiperclocks? ics p in a ssignment 0 1 1 0 phase detector vco 18 24 32 (default) 40 n 1 2 3 4 (default) 8 m osc 3 ics843004-02 24-lead tssop 4.40mm x 7.8mm x 0.92mm package body g package top view nq1 q1 v cc o q0 nq0 mr npll_sel nc nc v cca f_sel0 v cc 1 2 3 4 5 6 7 8 9 10 11 12 nq2 q2 v cco q3 nq3 f_sel2 nxtal_sel ref_clk v ee xtal_in xtal_out f_sel1 24 23 22 21 20 19 18 17 16 15 14 13 b lock d iagram npll_sel xtal_in xtal_out ref_clk nxtal_sel mr f_sel0:2 q0 nq0 q1 nq1 q2 nq2 q3 nq3 pulldown pulldown pulldown pulldown stupni redividm eulav redividn eulav 2les_ f1 les_ f0 les_f 000 8 13 00 1 4 24 010 4 28 011 2 31 10 0 2 32 10 1 2 34 110 2 38 111 0 48 f unction t able
idt ? / ics ? 3.3v lvpecl frequency synthesizer 2 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer t able 1. p in d escriptions t able 2. p in c haracteristics rebmu ne ma ne py tn oitpircsed 2, 11 q,1q nt uptu o. slevelecafretnilcepvl.riaptuptuolaitnereffid 22, 3v occ rewo p. snipylppustuptuo 5, 40 qn,0 qt upu o. slevelecafretnilcepvl.riaptuptuolaitnereffid 6r mt upn in wodllup erasredividlanretnieht,hgihcigolnehw.teserretsamhgihevitca xqnstuptuodetrevniehtdnawologotxqstuptuoeurtehtgnisuacteser erastuptuoehtdnasredividlanretnieht,wolcigolnehw.hgihogot .slevelecafretnilttvl/somcvl.delbane 7l es_llp nt upn in wodllup nehw.sredividehtottupnisaklc_ferdnallpehtneewtebstceles kcolcecnereferehtstceles,hgihnehw.)elbanellp(llpstceles,wol .slevelecafretnilttvl/somcvl.)ssapybllp( 9, 8c nd esun u. tcennocon 0 1v acc rewo p. nipylppusgolana ,11 91 ,0les_f 2les_f tupn ip ullu p. slevelecafretnilttvl/somcvl.sniptcelesycneuqerf 2 1v cc rewo p. nipylppuseroc 3 11 les_ ft upn in wodllu p. slevelecafretnilttvl/somcvl.sniptcelesycneuqerf ,41 51 ,tuo_latx ni_latx tupni ,tuptuoehtsituo_latx.ecafretnilatsyrctnanoserlellarap .tupniehtsini_latx 6 1v ee rewo p. nipylppusevitagen 7 1k lc_fe rt upn in wodllu p. tupnikcolcecnereferlttvl/somcvl 8 1l es_latx nt upn in wodllup ecnereferllpehtehtsastupniklc_ferrolatsyrcneewtebstceles .hgihnehwklc_ferstceles.wolnehwstupnilatxstceles.ecruos .slevelecafretnilttvl/somcvl 12,0 23 q,3q nt uptu o. slevelecafretnilcepvl.riaptuptuolaitnereffid 42,3 22 qn,2 qt uptu o. slevelecafretnilcepvl.riaptuptuolaitnereffid :eton pullupdnanwodllup .seulavlacipytrof,scitsiretcarahcnip,2elbatees.srotsisertupnilanretniotsrefer lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu c ni ecnaticapactupni 4f p r nwodllup rotsisernwodlluptupni 1 5k r pullup rotsiserpulluptupni 1 5k
idt ? / ics ? 3.3v lvpecl frequency synthesizer 3 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer t able 3. o utput c onfiguration and f requency r ange f unction t able stupni redividm eulav redividn eulav ocv )zhm( tuptuo ycneuqerf )zhm( noitacilppa 2les_ f1 les_ f0 les_ fk lc_fer 010 5 7.4 24 28 4 9 55 2.4 7v tdh 11 1 9 461538.4 10 48 6 604.39 55 428571.4 7v tdh 111 6 10 48 0 4 60 8i scs 10 1 4 4.9 12 34 8 0.22 62 5.55 1t enos 110 4 4.9 12 38 8 0.22 66 7.7 7t enos 011 4 4.9 12 31 8 0.22 68 0.22 6t enos 10 0 4 4.9 12 32 8 0.22 64 0.11 3t enos 00 1 5 24 24 0 0 60 5 1a tas 010 5 24 28 0 0 65 7a tas 00 1 5 265.6 24 24 5 .73 65 73.95 1l ennahcerbifgig01 10 1 5 2135.9 12 34 5 2 65 2.65 1t enrehtegig01 00 0 5 2.1 38 13 5 .26 55 .78 1t enrehtegig21
idt ? / ics ? 3.3v lvpecl frequency synthesizer 4 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 70c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, ta = 0c to 70c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, ta = 0c to 70c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v hi egatlovhgihtupni 2v cc 3.0 +v v li tupni egatlovwol ,les_latxn,les_llpn rm,2les_f:0les_f 3.0 -8 . 0v klc_fe r3 .0 -3 . 1v i hi tupni tnerruchgih 1les_f,rm,klc_fer les_latxn,les_llpn v cc v= ni v564.3 =0 5 1a 2les_f,0les_ fv cc v= ni v564.3 =5 a i li tupni tnerrucwol 1les_f,rm,klc_fer ,les_latxn,les_llpn v cc v,v564.3= ni v0 =0 51 -a 2les_f,0les_ fv cc v,v564.3= ni v0 =5 -a lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v cc egatlovylppuseroc 531. 33 . 35 64. 3v v acc egatlovylppusgolan av cc 21.0 ?3 . 35 64. 3v v occ egatlovylppustuptuo 531. 33 . 35 64. 3v i ee tnerrucylppusrewop 05 1a m i acc tnerrucylppusgolana 2 1a m
idt ? / ics ? 3.3v lvpecl frequency synthesizer 5 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer t able 6. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, ta = 0c to 70c t able 5. c rystal c haracteristics t able 4c. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, ta = 0c to 70c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v ho 1eton;egatlovhgihtuptu ov occ 4.1 -v occ 9.0 -v v lo 1eton;egatlovwoltuptu ov occ 0.2 -v occ 7.1 -v v gniws gniwsegatlovtuptuokaep-ot-kaep 6. 00 . 1v 05htiwdetanimretstuptuo:1eton vot occ .v2- retemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu noitallicsofoedom latnemadnu fz hm ycneuqerf 4 18 7.7 3z hm )rse(ecnat siserseirestnelaviuqe 05 ecnaticapactnuhs 7f p levelevird 1w m .latsyrctnanoserlellarapfp81nagnisudeziretcarah c:eton lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu f tuo ycneuqerftuptuo 0 70 8 6z hm f ocv egnarkcolocvllp ]0:2{les_f 00 00 6 50 8 6z hm 000=]0:2{les_ f0 6 50 8 5z hm t )o(k s1 eton;wekstuptuo 5 2s p t )?(ti j3 ,2eton;rettijesahpsmr zhm02-zhk21,zhm25.55 11 9. 0s p zhm5.7-zhk009,zhm5 76 7. 0s p t r t/ f emitllaf/esirtuptu o% 08ot%0 20 0 20 0 5s p cd oe lcycytudtuptuo redividndd o6 44 5% redividnnev e8 42 5% .snoitidnocdaollauqehtiwdn asegatlovylppusemasehttastuptuoneewtebwekssadenifed:1eton .stniopssorclaitnereffidtuptuoehttaderusaem .tupnilatsyrcehtgnisuderusaemsirettijesahp:2eton .56dradnatscedejhtiwecnadroccanidenifedsiretemarapsiht:3eton
idt ? / ics ? 3.3v lvpecl frequency synthesizer 6 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer t ypical p hase n oise at 75mh z a t 3.3v 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 75mhz rms phase jitter (random) 900khz to 7.5mhz = 0.91ps (typical) o ffset f requency (h z ) 100 1k 10k 100k 1m 10m 100m dbc hz n oise p ower ? ? ? raw phase noise data phase noise result by adding sata/sas filter to raw data sata/sas jitter filter t ypical p hase n oise at 155.52mh z a t 3.3v 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 155.52mhz rms phase jitter (random) 12khz to 20mhz = 0.91ps (typical) o ffset f requency (h z ) 100 1k 10k 100k 1m 10m 100m dbc hz n oise p ower ? ? ? raw phase noise data phase noise result by adding oc sonet filter to raw data oc sonet jitter filter
idt ? / ics ? 3.3v lvpecl frequency synthesizer 7 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer p arameter m easurement i nformation t pw t period t pw t period odc = x 100% q0:q3 rms p hase j itter o utput s kew 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v0.165v o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g v cc , v cco v ee nq0:nq3 o utput d uty c ycle /p ulse w idth /p eriod t sk(o) qy qx nqy nqx phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power v cca 2v
idt ? / ics ? 3.3v lvpecl frequency synthesizer 8 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843004-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10f and a .01 f bypass capacitor should be connected to each v cca . p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc i nputs : c rystal i nput : for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. ref_clk i nput : for applications not requiring the use of the test clock, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the ref_clk to ground. s elect p ins : all select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
idt ? / ics ? 3.3v lvpecl frequency synthesizer 9 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer c rystal i nput i nterface the ics843004-02 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below figure 2. c rystal i npu t i nterface were determined using an 18pf parallel resonant crystal and were chosen to minimize the ppm error. lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output impedance of the driver (ro) plus the series resistance (rs) equals f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xtal _i n xtal _ou t .1uf rs c1 27p xtal_out xtal_in c2 33p x1 18pf parallel crystal
idt ? / ics ? 3.3v lvpecl frequency synthesizer 10 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer t ermination for 3.3v lvpecl o utput v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating fre- quency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
idt ? / ics ? 3.3v lvpecl frequency synthesizer 11 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer l ayout g uideline figure 5 shows an example of ics843004-02 application schematic. in this example, the device is operated at v cc = 3.3v. the decoupling capacitor should be located as close as possible to the power pin. both input options are shown. the device can either be driven using a quartz crystal or a to logic input pins vcc rd2 1k c3 0.1uf r5 50 ro ~ 7 ohm q1 driv er_lvcmos c2 33pf vcc rd1 not install mr f_sel2 zo = 50 ohm + - c3 10uf ru1 1k vcco x1 19.44mhz to logic input pins zo = 50 ohm c1 0.1uf vcco set logic input to '1' vdd f_sel1 f_sel0 u4 843004-02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 nq1 q1 vcco q0 nq0 mr npll_sel nc nc vcca f_sel0 vcc f_sel1 xtal_out xtal_in vee test_clk nxtal_sel f_sel2 nq3 q3 vcco q2 nq2 (u1-3) r7 50 + - c2 0. 1uf logic control input examples zo = 50 ohm zo = 50 ohm r8 43 r2 10 r5 133 vcco=3.3v optional y-termination npll_sel c4 0.01u r4 82.5 r6 82.5 r6 50 vdd c1 27pf 3.3v vcca nxtal_sel (u1-12) vcc set logic input to '0' r3 133 vcc zo = 50 ohm vcc=3.3v 18pf ru2 not install (u1-22) 3.3v lvcmos signal. for the lvpecl output drivers, only two termination examples are shown in this schematic. additional termination approaches are shown in the lvpecl termination application note. f igure 5. ics843004-02 s chematic e xample
idt ? / ics ? 3.3v lvpecl frequency synthesizer 12 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843004-02. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843004-02 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 3.465v * 150ma = 519.75mw ? power (outputs) max = 32.8mw/loaded output pair if all outputs are loaded, the total power is 4 x 32.8mw = 131.2mw total power _max (3.465v, with all outputs switching) = 519.75mw + 131.2mw = 650.95mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 linear meter per second and a multi-layer board, the appropriate value is 65c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.651w * 65c/w = 112.3c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ? ? ja for 24- pin tssop, f orced c onvection ? ? ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 70c/w 65c/w 62c/w
idt ? / ics ? 3.3v lvpecl frequency synthesizer 13 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load. pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = (v oh_min /r l ) * (v dd_max - v oh_min ) pd_l = (v ol_max /r l ) * (v dd_max - v ol_max ) pd_h = (1v/50 ) * (2v - 1v) = 20mw pd_l = (0.4v/50 ) * (2v - 0.4v) = 12.8mw total power dissipation per output pair = pd_h + pd_l = 32.8mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
idt ? / ics ? 3.3v lvpecl frequency synthesizer 14 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer r eliability i nformation t ransistor c ount the transistor count for ics843004-02 is: 3467 t able 7. ja vs . a ir f low t able for 24 l ead tssop ? ? ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 70c/w 65c/w 62c/w
idt ? / ics ? 3.3v lvpecl frequency synthesizer 15 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer p ackage o utline - g s uffix for 24 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 lobmys sretemillim mumini mm umixam n4 2 a- -0 2.1 1 a5 0. 05 1.0 2 a0 8. 05 0.1 b9 1. 00 3.0 c9 0. 00 2.0 d0 7. 70 9.7 ec isab04.6 1 e0 3. 40 5.4 ec isab56.0 l5 4. 05 7.0 0 8 aa a- -0 1.0
idt ? / ics ? 3.3v lvpecl frequency synthesizer 16 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer t able 9. o rdering i nformation rebmunredro/tra pg nikra me gakca pg nigakcapgnippih se rutarepmet 20-ga400348sc i2 0a400348sc ip osstdael4 2e bu tc 07otc0 t20-ga400348sc i2 0a400348sc ip osstdael4 2l eer&epat005 2c 07otc0 fl20-ga400348sc il 20a400348sc ip osst"eerf-dael"dael4 2e bu tc 07otc0 tfl20-ga400348sc il 20a400348sc ip osst"eerf-dael"dael4 2l eer&epat005 2c 07otc0 .tnailpmocshoreradnanoitarugifnoceerf-bpehterarebmuntrapehtotxiffus"fl"nahtiwderedroeratahtstrap:eton while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use i n life support devices or critical medical instruments.
idt ? / ics ? 3.3v lvpecl frequency synthesizer 17 ics843004AG-02 rev a july 30, 2007 ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer teehsyrotsihnoisiver ve re lba te ga pe gnahcfonoitpircse de tad a1 t2 . noitpircsedles_llpndetcerroc-elbatnoitpircsednip 60/52/9 a9 t6 1s gnikrameerfdaeldedda-elbatnoitamrofnigniredro 70/03/7
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, the idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics843004-02 crystal-to-3.3v lvpecl frequency synthesizer

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